Array split across three-dimensional interconnected chips
US7420832B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2007 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Apr 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storage array has a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.