Semiconductor integrated circuit and leak current reducing method
US7420857B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2006 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Mar 1, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor integrated circuit device which includes at least an SRAM memory cell array comprising a plurality of memory cells each constituted of a circuit including load MOS transistors, drive MOS transistors and transfer MOS transistors, a substrate bias generating circuit which is electrically connected to the load MOS transistors and supplies a substrate potential to the load MOS transistors during at least operation and standby, and a source bias generating circuit which is electrically connected to the drive MOS transistors and supplies a source potential to the drive MOS transistors at standby. It is possible to reduce a leak current in an SRAM memory cell during both operation and standby and reduce current consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.