Method and apparatus of inter-chip bus shared by message passing and memory access
US7420977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2001 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Jul 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5682
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The first switch is connected to the first interface of the memory/command bus. The second switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The second switch is connected to the second interface of the memory/command bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.