Instruction set for efficient bit stream and byte stream I/O
US7421561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2003 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Jul 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method provide unaligned load/store functionality for a processor that supports only aligned load/store instructions. An exemplary embodiment includes an extension adapter including registers for storing data and load/store buffers for realigning data. A processor executes aligned load/store instructions that transfer data in multiples of bytes. Instructions are included for transferring data between memory and the load/store buffers, initializing and transferring data, initializing and transferring data in numbers of bits, advancing or offsetting a data pointer, and for flushing the load/store buffers. In a preferred embodiment, the extension adapter comprises a wide register file for buffering full words of data, load/store buffers formed from multiple single-bit registers for buffering data bits and streaming data for use by the processor, and address generators for pointing to data or memory addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.