Incrementing successive write operations to a plurality of memory devices
US7421564B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2006 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0813
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a given address range. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.