Device and method for managing a standby state of a microprocessor
US7421595B2 · kind B2 · utility
0Cited by
19References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 17, 2005 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | May 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3869
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a computation unit having logic units for executing operations associated with determined instructions of a microprocessor instruction set and a control unit for interpreting the instructions and for controlling the logic units accordingly. An internal timer of the microprocessor is activated by the control unit in response to the execution of a dedicated standby instruction of the microprocessor instruction set. Responsive thereto, a timeout signal is delivered to the control unit so as to place the microprocessor in a standby state during a determined timeout period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.