Chip development system enabled for the handling of multi-level circuit design data
US7421670B2 · kind B2 · utility
0Cited by
32References
35Claims
0Family size
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Key dates
| Filing date | Oct 28, 2005 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Oct 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for implementation of look-ahead design methodology. Efficient debugging of a design is accomplished by evaluating the high level register transfer level (RTL) representation of a device being designed by quickly simulating the downstream implementation of that device to expose potential implementation problems that would otherwise be found much later in the design or manufacturing cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.