Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric
US7423453B1 · kind B1 · utility
10Cited by
73References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 20, 2006 |
| Grant date | Sep 9, 2008 |
| Priority date | — |
| Expiry date | Mar 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Efficient layout schemes to implement switching networks of an interconnection fabric in an integrated circuit to connect two sets of conductors through rows of switches with prescribed number of tracks over the switching area are described. The layout schemes can be used repeatedly for multiple-stage switching network and/or hierarchically arranged switching networks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.