Multiple sampling sample and hold architectures
US7423458B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 2006 |
| Grant date | Sep 9, 2008 |
| Priority date | — |
| Expiry date | May 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sample and hold circuit architecture samples using two capacitors that are cyclically switched between charge and discharge modes. The sample and hold circuit includes a buffer to receive an input signal to be sampled, a first sampling capacitor, a second sampling capacitor, and an amplifier. The first sampling capacitor is connected to the output of the buffer during the positive phase of a clock and across the feedback path of the amplifier during the zero phase of the clock. The second sampling capacitor is connected to the output of the buffer during the zero phase of the clock and across the feedback path of the amplifier during the positive phase of the clock. Neither the first sampling capacitor nor the second sampling capacitor is simultaneously connected to the buffer, the amplifier, or to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.