Pipelined accumulators
US7424503B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2003 |
| Grant date | Sep 9, 2008 |
| Priority date | — |
| Expiry date | Feb 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Pipelined digital accumulators. Parallel digital accumulators for use in digital signal processing are improved through pipelining. An accumulator is partitioned into a plurality of pipelined stages, and the pipeline delay is used to reduce the effect of carry propagation through the accumulator. While input and output delay registers are used in the accumulator partitions, the output delay registers are not needed if the results of those partitions are not needed in subsequent stages of computation. If phase coherence is not needed, input delay registers may not be needed on accumulator partitions. In the limiting case of one bit per partition, the effective speed of the pipelined accumulator is equivalent to the speed of a single bit accumulator stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.