Architecture and related methods for efficiently performing complex arithmetic
US7424506B2 · kind B2 · utility
0Cited by
6References
28Claims
0Family size
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Key dates
| Filing date | Mar 31, 2001 |
| Grant date | Sep 9, 2008 |
| Priority date | — |
| Expiry date | Mar 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is presented comprising analyzing two or more input terms on a per-bit basis within each level of bit-significance. Maximally segmenting each of the levels of bit-significance into one or more one-, two-, and/or three-bit groups, and designing a hyperpipelined hybrid Wallace tree adder utilizing one or more full-adders, half-adders, and associated register based, at least in part, on the maximal segmentation of the input terms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.