Multiple level minimum logic network
US7426214B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 16, 2004 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | May 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network or interconnect structure 100 utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes 102 in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided. The interconnect structure operates as a “deflection” or “hot potato” system in which processing and storage overhead at each node is minimized. Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying overall control components and network interconnect components 104 and improving speed performance of message communication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.