Apparatus, system, and method for bus link width optimization of a graphics system
US7426597B1 · kind B1 · utility
75Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Sep 16, 2005 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Sep 16, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.