Switch for bus optimization
US7426602B2 · kind B2 · utility
7Cited by
36References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2005 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Aug 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.