Virtual output buffer architecture
US7426604B1 · kind B1 · utility
42Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2006 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Mar 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffer architecture enables linked lists to be used to administer virtual output queue buffering. The buffer has three random access memories (RAMs). A data RAM holds data. A free RAM holds a linked list of entries defining free space in the data RAM. Destination RAM holds a linked list of entries defining data in the data RAM to be forwarded to a destination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.