Method and apparatus for optimizing flash device erase distribution
US7426605B2 · kind B2 · utility
3Cited by
9References
19Claims
0Family size
Inventor
Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Jun 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A remapping circuit is connected to a memory. A configuration register is connected to the memory. The configuration register includes performance information for memory blocks in the memory. Also, a system includes a processor, a memory management device is connected to the processor, a display is connected to the processor, a non-volatile memory including a memory blocks is connected to the memory management device, and a register is connected to the non-volatile memory. The memory management device to re-map the non-volatile memory based on information stored in the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.