Computer system and fault processing method in computer system
US7426662B2 · kind B2 · utility
4Cited by
11References
4Claims
0Family size
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Key dates
| Filing date | Mar 14, 2005 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Oct 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A manager transmits an I/O bus signal to an I/O bus manager in a computer at a predetermined point of time to inform the I/O bus manager of occurrence of an I/O bus fault. The I/O bus manager initializes an I/O bus and then informs a CPU in the computer of the I/O bus fault as an interruption to be processed by an OS operated by the CPU, whereby the OS can acquire the fault information after the interruption even in the case where an I/O bus fault occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.