Noisy channel emulator for high speed data

US7426666B2 · kind B2 · utility

Assignee

• LUCENT TECHNOLOGIES INC. · US

Inventors

• Raul Benet Ballester · Premià de Mar, ES
• Adriaan J. De Lind Van Wijngaarden · New Providence, US
• Ralf Dohmen · Nuremberg, DE
• Bernd Dotterweich · Hirschaid, DE
• Swen Wunderlich · Dresden, DE

Key dates

• Filing date: May 18, 2004
• Grant date: Sep 16, 2008
• Expiry date: Jul 4, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L1/241
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.