Dynamic random access memory having at least two buffer registers and method for controlling such a memory
US7426675B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2004 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Aug 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory circuit including a memory plane composed of an array of memory cells arranged in lines and columns, and a line decoder, each line of the memory plane corresponding to a page of words. Two buffer registers are coupled with the memory plane for reading words in a page of the memory and for writing new words to a page of the memory, and the registers are used alternatively to access this memory plane. The buffer registers are dual-port memories and, moreover, the memory has an error correcting circuit allowing read-modify-write cycles applied to a group of n words within the same page. Whereby the reliability of the memory circuit is substantially increased and, moreover, an alternative solution to burn-in can even be offered. The invention also provides a method for controlling a dynamic memory having an error correcting code mechanism.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.