Method for fabricating isolation structures for flash memory semiconductor devices

US7427552B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Da Jin · Tianqiaoling, CN
• Shu Shu Tang · Shanghai, CN
• Zuo Ya Yang · Shanghai, CN

Key dates

• Filing date: Nov 2, 2006
• Grant date: Sep 23, 2008
• Expiry date: Jan 31, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76232
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for fabricating integrated circuit devices, e.g., Flash memory devices, embedded Flash memory devices. The method includes providing a semiconductor substrate, e.g., silicon, silicon on insulator, epitaxial silicon. In a specific embodiment, the semiconductor substrate has a peripheral region and a cell region. The method includes forming a first dielectric layer (e.g., silicon dioxide) having a first thickness overlying a cell region and a second dielectric layer (e.g., silicon dixode) having a second thickness overlying the peripheral region. In a specific embodiment, the cell region is for Flash memory devices and/or other like structures. The method forms a pad oxide layer overlying the first dielectric layer and forms a nitride layer overlying the pad oxide layer. The method includes patterning at least the nitride layer to expose a first trench region in the peripheral region and to expose a second trench region in the cell region, while a portion of the first dielectric layer having the first thickness in the cell region is maintained. The method includes forming a first trench structure having a first depth in the first trench region, while the portion of the first…