Guardringed SCR ESD protection
US7427787B2 · kind B2 · utility
20Cited by
5References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 8, 2005 |
| Grant date | Sep 23, 2008 |
| Priority date | — |
| Expiry date | Jul 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
Abstract
Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an associated microelectronic circuit for which ESD protection is desired. The SCR used in the ESD cell of the invention is provided with a full guardring for shielding the SCR from triggering by fast transients. A resistor is provided at the guardring for use in triggering the SCR at the onset of an ESD event. Exemplary preferred embodiments of the invention are disclosed with silicide-block resistors within the range of about 2-1000 Ohms or less.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.