Method for automated at-speed testing of high serial pin count multiple gigabit per second devices
US7428679B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 2005 |
| Grant date | Sep 23, 2008 |
| Priority date | — |
| Expiry date | May 30, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31924
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.