Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI)
US7429880B2 · kind B2 · utility
17Cited by
12References
18Claims
0Family size
Inventors
Key dates
| Filing date | Aug 11, 2003 |
| Grant date | Sep 30, 2008 |
| Priority date | — |
| Expiry date | Sep 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon and the like or Sapphire and the like including a method of synthesis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.