Buffer circuit with enhanced overvoltage protection
US7430100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2005 |
| Grant date | Sep 30, 2008 |
| Priority date | — |
| Expiry date | Jul 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit having enhanced overvoltage protection includes core buffer circuitry couplable to a first voltage source having a first voltage level. The core buffer circuitry is configured to receive a first signal and to generate a second signal which is a function of the first signal. The buffer circuit further includes a protection circuit coupled between the core buffer circuitry and a signal pad. The protection circuit is operative: (i) to clamp the first signal to about the first voltage level when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.