Method and apparatus for performing multiply-add operations on packed byte data
US7430578B2 · kind B2 · utility
90Cited by
151References
32Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 30, 2003 |
| Grant date | Sep 30, 2008 |
| Priority date | — |
| Expiry date | Mar 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.