Devices for performing multiple independent hardware acceleration operations and methods for performing same
US7430652B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2003 |
| Grant date | Sep 30, 2008 |
| Priority date | — |
| Expiry date | Apr 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4843
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.