Zeroing circuit for performance counter
US7430696B2 · kind B2 · utility
3Cited by
10References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2003 |
| Grant date | Sep 30, 2008 |
| Priority date | — |
| Expiry date | Sep 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the invention is directed to a zeroing circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The zeroing circuit comprises logic for zeroing out a specified number of most significant bits (“MSBs”) of a selected portion of the debug data based on a mask generated by a mask generator block. A selection control signal provided to the mask generator block is operable to be decoded to a particular mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.