Method for forming a transistor for reducing a channel length
US7432144B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Feb 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorphous region at a lower part of both sidewalls of the gate polysilicon layer pattern; reducing a channel length by removing the amorphous region so as to form a notch at a lower part of both sidewalls of the gate polysilicon layer pattern; forming a gate spacer at both sidewalls of the gate polysilicon layer pattern; and forming a high energy ion implantation region by high energy ion implantation of source/drain impurities into an entire surface of the silicon substrate including the gate polysilicon layer pattern and gate spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.