Methods of forming a recessed gate
US7432155B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 18, 2006 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Oct 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/027
Abstract
A method of forming a recessed gate may include forming a gate recess including an upper recess and a lower recess at an upper portion of a semiconductor substrate, the lower recess may have a width substantially wider than that of the upper recess, forming a gate insulation layer on an inner surface of the gate recess, forming a first silicon layer on the semiconductor substrate including the gate insulation layer to form an open void within the gate recess, forming a stop layer having a high thermal resistance on the first silicon layer to prevent a void from moving around within the gate recess, forming a second silicon layer on the first silicon layer, and patterning the second and the first silicon layers to form a gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.