Semiconductor devices including transistors having three dimensional channels and methods of fabricating the same
US7432160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2007 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Apr 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.