Duty cycle stabilizer
US7432752B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2007 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Apr 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00039
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle stabilizer circuit (50) receiving an input clock signal and generating an output clock signal having a first duty cycle includes a leading edge pulse generator (52) and a pulse width extender circuit (54). The pulse generator generates a first clock pulse (V1) having a leading edge triggered by the leading edge of the input clock signal and a first pulse width. The pulse width extender circuit generates a second clock pulse (V2) having a leading edge triggered by the leading edge of the first clock pulse and a pulse width being stretched to the desired duty cycle. The duty cycle stabilizer further includes a buffer (64) providing the output clock signal having the first duty cycle, a charge pump (56) receiving the output clock signal directly and a differential amplifier (62) generating an output signal for controlling the pulse width of the first and second clock pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.