Solid-state imaging device with plural CDS circuits per column sharing a capacitor and/or clamping transistor
US7432964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2004 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Aug 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A solid-state imaging device includes a pixel array area having pixels including photoelectric transducers arranged as an array; signal lines wired for every pixel column in the pixel array area; and a plurality of noise reducers provided for the corresponding signal lines. Each of the noise reducers includes a first capacitor, one end of which is connected to the signal line; a first switch element, an input port of which is connected to the other end of the first capacitor; a second capacitor connected between an output port of the first switch element and a reference voltage; and a clamping element for clamping the voltage of a connecting node between the output port of the first switch element and the second capacitor to a predetermined voltage. The first capacitor is shared among the plurality of noise reducers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.