Memory with reduced bitline leakage current and method for the same
US7433239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Aug 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory includes a plurality of access transistors with each of the access transistors coupled to one of the wordlines at its control terminal and connected to one of the bitlines at its output terminal. A plurality of memory cells have each output coupled to an input terminal of one of the access transistors so that the access transistors share one of the wordlines and are coupled to different bitlines. A wordline driver coupled to each wordline has the ability of generating a variable voltage at its output responsive to the wordline driver control inputs and voltage at its ground supply node. A plurality of grouped voltage supply lines are coupled to a group of the wordline drivers for inducing a variable reference voltage or ground supply at the ground supply node. A voltage switching logic switches the voltage for the variable ground supply responsive to a ground control input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.