Adaptive hysteresis receiver for a high speed digital signal
US7433426B2 · kind B2 · utility
2Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 23, 2004 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | May 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.