Reducing flicker noise in two-stage amplifiers
US7433656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2006 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Apr 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-stage amplifier includes first and second amplification stages and a loading stage, all of which generate flicker noise. A degeneration block is operably disposed between circuit common and the loading stage wherein the degeneration block is operable to reduce flicker noise generated by at least one of the loading stage, the first amplification stage and the second amplification stage. The degeneration block further includes at least one active MOSFET operably biased in a linear region to provide a specified resistive value and coupled to receive and conduct the common mode portion of the intermediate stage output signal based upon a gate terminal bias signal. A degeneration block amplifier is operable to generate a replica device bias signal wherein the replica device is operable to set the gate terminal bias signal for the at least one active MOSFET based upon the replica device bias signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.