DMAC to handle transfers of unknown lengths
US7433977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2006 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Apr 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DMA controller maintains a count of data transferred in each DMA operation, and saves the transferred data count at the end of the DMA operation. The DMA controller may then begin a subsequent DMA transfer operation, without waiting for a processor to read the transferred data count. The transferred data count may be written to memory at an address specified in a transferred data count save address register; may be saved to a transferred data count register dedicated to the DMA channel; or may be saved to a transferred data count register shared between two or more DMA channels. The processor may read the transferred data count and, if applicable, clear the relevant transfer data count register, subsequent to the DMA controller beginning another DMA operation on that DMA channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.