Method and apparatus for eliminating sampling errors on a serial bus
US7434084B1 · kind B1 · utility
2Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2005 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Mar 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous bit-serial data interface utilizes a transmitter that transmits a data stream having duplicates of each data bit. The receiver samples the data stream utilizing either the rising or falling edge of a received clock signal. If the rising edge is utilized the first duplicated bit is discarded and if the falling edge is utilized the second duplicated bit is discarded. The system allows transmitter/receiver pairs of devices that sample and latch data on the same clock edge to communicate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.