Polish stop and sealing layer for manufacture of semiconductor devices with deep trench isolation
US7435661B2 · kind B2 · utility
53Cited by
7References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2006 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | May 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/763
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and resulting device that eliminates vertical steps or gaps in a deep trench isolation region and, thus, eliminates or drastically reduces a possibility of polysilicon stringers. Additionally, the invention allows an inexpensive dielectric material, for example a lower-quality silicon dioxide to be used to fill the deep trench and a higher quality oxide, in an electrically active region, to be used on an uppermost portion of the deep trench without affecting device performance or increasing a possibility of forming polysilicon stringers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.