Tailoring via impedance on a circuit board
US7435912B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2002 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jul 28, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit board includes multiple signal layers, in which signal lines are routed, and reference plane layers, in which power reference planes are provided. To connect signal lines at different signal layers, vias are passed through at least one signal layer and at least one reference plane layer. At the one signal layer, a first clearance (or anti-pad) is defined around the via. At the reference plane layer, a second clearance is defined around the via. The second clearance is larger in size than the first clearance to match the impedance of the via as closely as possible with the impedance of a signal line the via is electrically connected to.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.