Process for fabricating a heterostructure-channel insulated-gate field-effect transistor, and the corresponding transistor
US7436005B2 · kind B2 · utility
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2References
22Claims
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Key dates
| Filing date | Sep 15, 2005 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jan 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
Abstract
The insulated-gate field-effect transistor includes a substrate surmounted by a layer of silicon-germanium alloy, the ratio of the germanium concentration to the silicon concentration of which increases towards the surface of the substrate. The transistor is formed on the active zone in the silicon-germanium alloy layer and lies between two isolating zones. The transistor includes a narrow heterostructure strained-semiconductor channel including a SiGe alloy layer in compression and a silicon layer in tension, extending between the gate and a dielectric block buried in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.