Packaging substrate and semiconductor device
US7436063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2005 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jan 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01078
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate and comprises a wiring provided on a bonding surface to which the semiconductor chip is bonded, a plurality of electrode parts provided on the bonding surface and electrically connected to the wiring, a wiring protective layer for coating and protecting the wiring, electrode openings formed by partly opening the wiring protective layer for separately exposing each of the electrode parts from the wiring protective layer, and escape openings each formed in continuation with each of the electrode openings in the wiring protective layer for introducing therein a part of the connection metal body to be connected to each of the electrode parts to escape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.