Architecture for reducing leakage component in semiconductor devices
US7436201B2 · kind B2 · utility
3Cited by
2References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Dec 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An architecture for reducing leakage component in semiconductor devices using a gated power supply is based on the supply being split into two parts. An alternate inverter is connected to a different power rail derived from the same single power rail. The power rails are enabled and disabled according to the value of a standby signal and an input signal. The standby signal is high in the standby mode and low in the active mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.