Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation
US7436229B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2007 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Sep 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.