Digital clock modulator
US7436235B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2004 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jun 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2215/067
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected in series and receiving as an input an unmodulated clock signal. A multiplexer receives inputs from unequally spaced taps between the delay elements. A control block provides selection inputs to the multiplexer, and receives the unmodulated clock signal from the delay elements. The delay elements include a last delay element providing the unmodulated clock signal to the control block. The last delay element has a predetermined delay for ensuring that the delay elements and related signal paths are in a same stable state before control to the multiplexer changes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.