Semiconductor memory device
US7436720B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2006 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Dec 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes plates accessed by different row addresses and a sense amplifier column between the adjacent plates. The sense amplifier column is a mixture of configurations, one in which one of the pair of bit lines is twisted, and another in which neither of the pair of bit lines is twisted. If an address analysis indicates that there is an access through an input/output wiring, input/output data is not inverted. If the address analysis indicates that there is an access through another input/output wiring and that it is an access to a plate, the input/output data is not inverted, while if it is an access to another plate, the input/output data is inverted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.