Timer based stall avoidance mechanism for high speed wireless communication system
US7436795B2 · kind B2 · utility
30Cited by
21References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2002 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Nov 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/1812
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This invention uses timers at the transmitter to track its sending data blocks to improve the timer-based stall avoidance mechanism of the prior art. Moreover, the invention uses a multi-timer mechanism to manage reordering buffers at the receiver. The multi-timer mechanism provides the receiver with one timer per reorder buffer, or uses one timer per missing data block, or uses one timer per missing data block but a gap of consecutive TSN missing data blocks can share one timer. The multi-timer mechanism can effectively track the missing blocks and monitor the reorder delivery process for all reordering buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.