Method and apparatus for wire-speed application layer classification of upstream and downstream data packets
US7436830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Sep 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/2441
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data packet classifier to classify a plurality of N-bit input tuples, said classifier comprising a hash address, a memory and a comparison unit. The hash address generator generate a plurality of M-bit hash addresses from said plurality of N-bit input tuples, wherein M is significantly smaller than N. The memory has a plurality of memory entries and is addressable by said plurality of M-bit hash addresses, each such address corresponding to a plurality of memory entries, each of said plurality of memory entries capable of storing one of said plurality of N-bit tuples and an associated process flow information. The comparison unit determines if an incoming N-bit tuple can be matched with a stored N-bit tuple. The associated process flow information is output if a match is found and wherein a new entry is created in the memory for the incoming N-bit tuple if a match is not found.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.