Cache memory with the number of operated ways being changed according to access pattern
US7437513B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 28, 2005 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Apr 14, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improvement in performance and a reduction of power consumption in a cache memory can both be effectively realized by increasing or decreasing the number of operated ways in accordance with access patterns. A hit determination unit determines the hit way when a cache access hit occurs. A way number increase/decrease determination unit manages, for each of the ways that are in operation, the order from the way for which the time of use is most recent to the way for which the time of use is oldest. The way number increase/decrease determination unit then finds the rank of the hit ways that have been obtained in the hit determination unit and counts the number of hits for each rank in the order. The way number increase/decrease determination unit further determines increase or decrease of the number of operated ways based on the access pattern that is indicated by the relation of the number of hits to each rank in the order. A way number control unit then selects operation or halt of operation for each way in accordance with the determination to increase or decrease the number of operated ways.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.