Testing memories
US7437531B2 · kind B2 · utility
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13References
8Claims
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Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Oct 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo random memory addresses, and a deterministic data generation unit, such as, for example, including a state machine, to generate deterministic data to be written to the pseudo random memory addresses. Computer systems and other electronic systems including such apparatus are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.