Complex domain floating point VLIW DSP with data/program bus multiplexer and microprocessor interface
US7437540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2004 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jun 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7857
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for digital signal processing, configured as a system on chip (SoC), combines a microprocessor core and digital signal processor (DSP) core with floating-point data processing capability. The DSP core can perform operations on floating-point data in a complex domain and is capable of producing real and imaginary arithmetic results simultaneously. This capability allows a single-cycle execution of, for example, FFT butterflies, complex domain simultaneous addition and subtraction, complex multiply accumulate (MULACC), and real domain dual multiply-accumulators (MACs). The SoC may be programmed entirely from a microprocessor programming interface, using calls from a DSP library to execute DSP functions. The cores may also be programmed separately. Capability for programming and simulating the entire SoC are provided by a separate programming environment. The SoC may have heterogeneous processing cores in which either processing core may act as master or slave, or both cores may operate simultaneously and independently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.